1. Field of the Invention
This invention relates in general to the design of integrated circuits (ICs), and in particular, to the optimization of standard-cell libraries used to synthesize and optimize ICs.
2. Description of the Related Art
In the design and manufacture of modern Integrated Circuits (ICs), as the transistor geometry has decreased with scaling, high power dissipation is a major concern to IC designers. Typically, leakage power, which is the power consumed by transistors when they are not actively switching, accounts for the major part of the total power consumption in ICs. It is estimated that leakage power accounts for over half of the total power consumption in the 65 nm IC fabrication process. Therefore, IC designers seek to improve the leakage power consumption of an IC without impacting its performance characteristics. In a modern IC design, pre-designed standard-cell libraries are stored in certain databases that provide the components from which an IC is synthesized and optimized. The leakage power consumption and the performance characteristics of the IC depend on the standard-cell library used. Therefore, integrated circuit optimization requires optimization of the standard-cell library.
Several circuit-optimization techniques have been developed to control the consumption of leakage power. Certain of these circuit-optimization techniques create an optimized IC by selectively replacing cells in an existing circuit. The cells are obtained from the standard-cell library. The leakage power and performance characteristics of the optimized IC depend on the quality of the optimizer and the cells available in the library. Some of these techniques are based on the fact that modifying (hereinafter referred to as ‘biasing’) the gate lengths of transistors by small amounts can reduce leakage power without significant penalties in timing, area or input capacitance, without extra manufacturing cost. Essentially, timing slack is traded off for leakage power. Such techniques, used in the past, assigned the same gate length to every transistor in a cell, which resulted in suboptimal utilization of the available timing slack. Further, assigning the same gate length does not take into account factors such as the difference in the mobility of electrons, which are the principal carriers in the NMOS transistors, and the mobility of holes, which are the principal carriers in the PMOS transistors. Other factors, such as the asymmetry of rise-time and fall-time slacks, are also ignored. Therefore, with respect to the previous techniques, it is possible to intelligently decrease the granularity of length assignment to improve timing-slack utilization.
Other existing leakage reduction techniques use multiple threshold voltage (Vth) libraries, where each cell has 2-3 different Vth variants. The variants are chosen for assignments to different paths, based on the available slack on the paths. These techniques require a separate masking step in the manufacturing process of the IC, for each different Vth. This makes such techniques expensive and limits the number of available threshold voltages to 2 or 3.
Therefore, there exists a need for a method and system that can selectively assign a bias to transistor parameters, such as the transistor gate-length and the threshold voltage of the individual transistors of the cells of a standard-cell library, to improve the leakage and performance of manufactured ICs.